1. Field of the Invention
The present invention relates generally to an apparatus which computes the delay time of an integrated circuit. More specifically, the present invention relates to an apparatus which computes changes in signal propagation delay time caused by the load of a cell used in designing a semiconductor integrated circuit and/or caused by the load connected to that cell.
2. Description of the Related Art
Despite the trend in integrated semiconductor circuit (IC) design to design ever larger scale circuits, circuit designers have also sought to increase the speed with which these increasingly large circuits operate. In designing a semiconductor integrated circuit, the timing of the cells used in the integrated circuit is very important. As circuit operation becomes faster, the accumulative signal delay time of the individual cells is a significant factor in design layout. Generally speaking, circuit delay time is the amount of time that an output signal follows an input signal. This delay time is directly affected by signal propagation delay time, i.e., the time required for a logic signal to travel through a device or series of logical devices. One component of signal propagation delay is rise time, i.e., the time needed for the leading edge of a pulse to rise from 10% to 90% of its final value. Should the individual component or component connections be such that cause a signal to experience a longer rise or propagation delay time, the circuit's overall delay time will increase, in effect slowing down circuit operation. Increases in a signal's rise time decreases the slope of the signal's voltage potential as it changes low to high or vice versa. Careful consideration to signal propagation and delay time is therefore necessary for proper layout design. Consequently, it is important to be able to quickly compute how variations in cell layout, or more particularly, in fan-out, affects individual cell delay time. That is, it is helpful to know how various loads or how various fan-outs affect cell delay time. This is necessary in order to shorten the time for designing a semiconductor integrated circuit.
FIG. 1 shows a conventional sequence of procedures used to compute the delay time of logic circuits in a semiconductor integrated circuit. This conventional computation is adapted for the circuit whose design has been completed. First, a designer combines a plurality of selected cells and designs a logic circuit 40 as shown in, for example, FIG. 2 based on his or her own experience by using a Computer Aided Design (CAD) system at step 51. The logic circuit 40 includes four AND gates 41, 42, 45 and 46, an OR gate 43 and an inverter 44. The AND gate 41 has two input terminals A and B, and an output terminal connected to the inverter 44. The AND gate 42 has two input terminals C and D. The AND gate 45 has two input terminals respectively connected to the output terminals of the inverter 44 and the AND gate 42. The 0R gate 43 has two input terminals E and F. The AND gate 46 has two input terminals respectively connected to the output terminals of the AND gate 45 and the OR gate 43, and an output terminal X.
After the design of the whole logic circuit is completed, the computer examines the design for potential signal propagation paths, i.e. individual paths extending from the associated input terminals A to F and reaching the output terminal X, at step 52. When a circuit simulation is executed, the computer computes the propagation delay times of signals for the individual paths, at step 53. The results of the computation are output on a display or a printer at step 54. The designer can know the delay times of the individual paths based on the computation results. When the computed delay time for any one of the paths does not meet design expectations or requirements, the designer alters the design of the logic circuit at step 55, and repeats the sequence of procedures of steps 52 to 54.
To realize the effect of variations in cell load or fan-out on circuit delay time requires circuit redesign, cell layout alteration, signal path reconnection and finally simulation of the new design. Using conventional techniques, this job involves a considerable amount of work and time.
As mentioned above, rise time delay occurs in signals traveling through the paths of logic circuits. FIG. 3A shows an input signal ISG exhibiting a unit step function. Signal ISG obviously contains no slope or rise time delay. FIGS. 3B, 3C and 3D, on the other hand, exhibit various rise time and turn on delays, i.e., various propagation delay characteristics. The output signal OSG shown in FIG. 3B has a specific delay time t1 caused, for example, by a logic gate cell. Additional cell interconnections may cause a turn on delay time t2 as in the signal ST shown in FIG. 3C. If signal is further propagated to one of two mutually coupled cells from the preceding cell, the output signal OPS of the succeeding cell is affected not only by a rise time delay, i.e. a decrease in the slope of the rising waveform, but also by further turn on delay. As shown in FIG. 3D, the rise time delay of signal OPS t3 is greater than either time t2 or t1, due to circuit layout redesign. The computation of the delay time involving the signal is mathematically complex, and is not usually performed manually by the designer.